1. Field of the Invention
The present invention relates to a field effect transistor. In particular, the invention relates to a junction gate field effect transistor with a high gate forward turn-on voltage, a large maximum drain current, and a low on-resistance.
2. Description of Related Art
A hetero-junction field effect transistor (FET: Field Effect Transistor) made of a III-V compound semiconductor, which is typified by HEMT (High electron mobility transistor), has been widely used as a low-noise, high-power, and high-efficiency device. Among transistors made of III-V compound semiconductor, GaAs or InP-made electronic devices are promising as ultrahigh-speed and high-frequency devices.
In order to enhance the performance of the field effect transistor made of the III-V compound semiconductor, a gate forward turn-on voltage (VF) needs to be increased. This is because an increase in VF leads to a higher gate voltage, so the maximum drain current that flows through the FET can be increased. Further, the increase in VF also leads to a decrease in leak current as a current amount at null voltage.
To increase the voltage VF, it is necessary to form a potential barrier as an electron barrier just below the gate such that no leak current flows even if a high voltage is applied to the gate electrode. If the potential barrier is small, the leak current flows at the time of applying the high voltage to the gate electrode, so an effective voltage applied to the gate electrode is lowered. Thus, the voltage VF cannot be increased.
A pn junction formed just below the gate electrode is utilized for forming the potential barrier below the gate. The pn junction enables a higher potential than a Schottky barrier resulting from the contact between metal and semiconductor. Therefore, it is conceivable that the VF can be increased by forming the pn junction just below the gate electrode of the FET.
To that end, there has been proposed an FET that is constructed to have the pn junction just below the gate electrode of the FET for increasing the voltage VF. As an example of the structure where the pn junction is defined just below the gate electrode, there has been known an FET where a gate recess structure is formed just below the gate electrode, and a p+-GaAs layer is formed in the gate recess structure (see Japanese Unexamined Patent Application Publication No. 2001-250939, for example).
In this FET, the p+ type semiconductor layer is buried into the gate recess structure, and the pn junction interface is defined closer to the substrate. Hence, a distance between the pn junction interface and the channel is reduced, so a threshold voltage is turned into a positive voltage (enhancement type), and the on-resistance can be reduced due to less influence of a surface depletion layer formed in the semiconductor layer adjacent to the gate electrode to the channel layer.
Further, in order to obtain the gate recess structure, an InGaP stopper layer formed below the gate recess structure is utilized. The reason why an InGaP layer is used as the stopper layer is that the barrier height of the InGaP layer in a conduction band is small, so a resistance of a current path from an ohmic electrode to the channel is lowered and thus, the on-resistance can be reduced.
FIG. 12 is a sectional view of a J-FET (Junction FET) 90 of the Related Art. Laminated on a GaAs substrate 911, an undoped GaAs layer 912, an undoped AlGaAs layer 913, an Si doped AlGaAs electron supply layer 914, an undoped AlGaAs spacer layer 915, an undoped InGaAs channel layer 916, an undoped AlGaAs spacer layer 917, an Si doped AlGaAs electron supply layer 918, an undoped AlGaAs layer 919, and an undoped InGaP gate recess stopper layer 920.
An undoped GaAs layer 921 is laminated on the undoped InGaP gate recess stopper layer 920. In the undoped GaAs layer 921, a gate recess structure 941 is formed. A C-doped p+-GaAs layer 924 is buried into the gate recess structure 941. The C-doped p+-GaAs layer 924 forms the pn junction. In addition, a gate electrode 927 is laminated on the C-doped p+-GaAs layer 924.
In addition, an Si doped AlGaAs wide recess stopper layer 922 and an Si doped GaAs cap layer 923 are layered on the undoped GaAs layer 921. A wide recess structure 942 is formed in the wide recess stopper layer 922 and the cap layer 923. A gate insulating film 928 is formed in the wide recess structure 942. Further, a drain electrode 925, and a source electrode 926 is formed on the Si doped GaAs cap layer 923.
However, in the J-FET 90 of the Related Art, when the p+-GaAs layer 924 grows in the gate recess structure 941, In of the undoped InGaP gate recess stopper layer 920 that contacts the bottom of the p+-GaAs layer 924 reacts with AsH3 as a material gas of the p+-GaAs layer 924 to form the InAs semiconductor layer. A band gap of this InAs semiconductor layer is smaller than the GaAs layer, AlGaAs layer and the InGaP layer, and its potential barrier with respect to electrons is low. Thus, recombination easily occurs in the InAs layer, and a recombination current flows.
Moreover, at the surface of the undoped InGaP gate recess stopper layer 920, an indium oxide layer such as In2O3 that is generated through the reaction between In extracted from this layer and oxygen is formed at the interface between the undoped InGaP gate recess stopper layer 920 and the p+-GaAs layer 924. The indium oxide has conductivity.
Based on the above, as shown in FIG. 12, a gate leak current 951 flows from the gate to a source or a drain through the aforementioned indium oxide or InAs semiconductor layer. A semiconductor layer positioned just below portions other than the recess structure of the wide recess structure, a depletion layer is formed up to the undoped InGaAs channel layer 916 due to a surface potential, so the gate leak current 951 flows from the p+-GaAs layer 924 to the undoped InGaAs channel layer 916, flows through a path similar to a drain current path, and flows into the drain electrode 925, and the source electrode 926. As a result, the gate forward turn-on voltage VF is decreased.
As another example of the Related Art, there is proposed a J-FET 91 that is formed using an InGaP stopper layer adjacent to the gate recess structure for forming the gate recess structure just below the gate electrode (see “Applied Physics Letters”, 1980, Vol. 37, pp. 163-165, for example. FIG. 13 is a sectional view of the J-FET 91 of the Related Art.
In the J-FET 91 of the Related Art, the gate recess structure 941 is obtained using the InGaP gate recess stopper layer 931 adjacent to the gate recess structure 941. In the J-FET 91, a side surface of the p+-GaAs layer 924 just below the gate electrode only contacts the InGaP gate recess stopper layer 931.
However, in the J-FET 91 structure as well, when the p+-GaAs layer 924 is formed just below the gate electrode such that the side surface thereof contacts the InGaP gate recess stopper layer 931, the indium oxide or InAs semiconductor layer is formed on the surface of the InGaP gate recess stopper layer 931. The gate leak current 951 flows through the indium oxide or InAs semiconductor layer formed on the surface of the InGaP gate recess stopper layer 931.
As mentioned above, at the time of forming the semiconductor layer that forms the pn junction just below the gate electrode, if the semiconductor layer containing In is used as the stopper layer, a gate leak current flows, making it impossible to increase the gate forward turn-on voltage VF.